25R256DYIG – GD25R256DYIG

SPI Mode
Standard SPI
The GD25R256D features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#),
Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the
rising edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The GD25R256D supports Dual SPI operation when using the “Dual Output Fast Read”, “Dual Output Fast Read with
4-Byte address”, “Dual I/O Fast Read” and “Dual I/O Fast Read with 4-Byte address” commands (3BH 3CH BBH and BCH).
These commands allow data to be transferred to or from the device at twice the rate of the standard SPI. When using the
Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1.
Quad SPI
The GD25R256D supports Quad SPI operation when using the “Quad Output Fast Read”, “Quad Output Fast Read
with 4-Byte address”, “Quad I/O Fast Read”, “Quad I/O Fast Read with 4-Byte address” (6BH, 6CH, EBH and ECH)
commands. These commands allow data to be transferred to or from the device at four times the rate of the standard SPI.
When using the Quad SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1, in addition to IO2 and
IO3 pins. For GD25R256D, QE bit is set to 1 as default and cannot be changed